SITAEL gained a large experience in the design, development, test and verification of processor modules based on LEON CPUs equipped with companion FPGAs. Moreover, specific skills have been matured also in the design of FPGA based HK systems exploiting SpaceWire and RMAP protocol. Boards and Units have been developed mainly for specific payloads data handling/processing needs, but can be exploited also for platform management.
In the frame of a contract with OHB-CGS, SITAEL is responsible for the development of the Power and Processing Unit of METIS (MPPU), the Coronagraph of the Solar Orbiter Mission. MPPU is composed of two Nominal + Redundant processor and power boards plus a common HK & IF board for a total of five modules and a passive backplane connecting them.
In the frame of a contract with ASI, SITAEL is developing the Central Processing Unit (CPU) and Power Conditioning and Distribution Module (PCDM) of Data Processing Unit (DPU) of the Solar Wind Analyzer (SWA) Instrument of Solar Orbiter Mission. DPU provides data processing and power supply to the four sensors named HIS, PAS, EAS of the instrument and is composed of Two Power Conditioning and Distribution Module (PCDM) operating in cold redundancy, Two DPU Processing Module (DPM) operating in cold redundancy and One Backplane including the electronic circuits of six “SpaceWire Splitters” (BSS).
IPPM is a flexible, programmable and modular system, able to operate as a real single board compact computer suitable for supporting requirements coming from different mission scenarios. It reduces the time to market improving capabilities and performances of space systems with more efficient design and manufacturing flows. IPPM board has been designed for missions where several payloads share a common DPU (Data Processing Unit). Moreover, its wide number of communication ports and the large amount of memory, combined with the LEON2 processor features, make it suitable to the majority of space missions.
SITAEL Telemetry/Telecommand (TMTC) is a communication device suitable for LEO orbits. The TMTC is capable to receive telecommands from Ground Station and send telemetry data to Earth at a datarate up to 153.6 kpbs. The digital architecture is based on ARM Cortex-M4 32 Bit microcontroller and is equipped with watchdog, OVP and SEL protection. It includes redundant CAN BUS and redundant RS-422 interfaces and up to 48 Mbytes of flash memory for data storage. Computing units have undergone TID ( > 30 Krads) and SEE test. SEU protection is implemented at board level.
SITAEL OBC is designed to host on-board data handling and AOCS computation functionality. It is developed as part of the low-cost product line for small LEO platforms and technological demonstrators. SITAEL OBC is built around a 32-bit ARM Cortex M4, equipped with the peripheral required to communicate with sensors and actuators.